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1. general description the 74ahc259; 74ahct259 is a high-speed si-gate cmos device and is pin compatible with low-power schottky ttl (lsttl). it is speci?ed in compliance with jedec standard no. 7-a. the 74ahc259; 74ahct259 is a high-speed 8-bit addressable latch designed for general purpose storage applications in digital systems. it is a multifunctional device capable of storing single-line data in eight addressable latches and providing a 3-to-8 decoder and multiplexer function with active high outputs (q0 to q7). it also incorporates an active low common reset ( mr) for resetting all latches as well as an active low enable input ( le). the 74ahc259; 74ahct259 has four modes of operation: ? in the addressable latch mode, data on the data line (d) is written into the addressed latch. the addressed latch will follow the data input with all non-addressed latches remaining in their previous states. ? in the memory mode, all latches remain in their previous states and are unaffected by the data or address inputs. ? in the 3-to-8 decoding or demultiplexing mode, the addressed output follows the state of the data input (d) with all other outputs in the low state. ? in the reset mode, all outputs are low and unaffected by the address inputs (a0 to a2) and data input (d). when operating the 74ahc259; 74ahct259 as an address latch, changing more than one bit of the address could impose a transient-wrong address. therefore, this should only be done while in the memory mode. 2. features n balanced propagation delays n all inputs have schmitt-trigger actions n combines demultiplexer and 8-bit latch n serial-to-parallel capability n output from each storage bit available n random (addressable) data entry n easily expandable n common reset input n useful as a 3-to-8 active high decoder n inputs accept voltages higher than v cc 74ahc259; 74ahct259 8-bit addressable latch rev. 02 15 may 2008 product data sheet
74ahc_ahct259_2 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 02 15 may 2008 2 of 17 nxp semiconductors 74ahc259; 74ahct259 8-bit addressable latch n input levels: u for 74ahc259: cmos level u for 74ahct259: ttl level n esd protection: u hbm eia/jesd22-a114e exceeds 2000 v u mm eia/jesd22-a115-a exceeds 200 v u cdm eia/jesd22-c101c exceeds 1000 v n multiple package options n speci?ed from - 40 c to +85 c and from - 40 c to +125 c 3. ordering information 4. functional diagram table 1. ordering information type number package temperature range name description version 74ahc259 74ahc259d - 40 c to +125 c so16 plastic small outline package; 16 leads; body width 3.9 mm sot109-1 74ahc259pw - 40 c to +125 c tssop16 plastic thin shrink small outline package; 16 leads; body width 4.4 mm sot403-1 74ahct259 74ahct259d - 40 c to +125 c so16 plastic small outline package; 16 leads; body width 3.9 mm sot109-1 74ahct259pw - 40 c to +125 c tssop16 plastic thin shrink small outline package; 16 leads; body width 4.4 mm sot403-1 fig 1. logic symbol fig 2. iec logic symbol mna573 d a0 a1 a2 mr le q0 q1 q2 q3 q4 q5 q6 q7 14 15 12 11 10 9 7 6 5 4 3 2 1 13 mna572 1 9,10d z9 g8 g10 c10 8r 13 15 14 0 1 2 3 1 2 0 dx 0 7 2 3 4 5 4 6 7 9 10 11 12 5 6 7 g
74ahc_ahct259_2 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 02 15 may 2008 3 of 17 nxp semiconductors 74ahc259; 74ahct259 8-bit addressable latch 5. pinning information 5.1 pinning 5.2 pin description fig 3. functional diagram mna571 8 latches 1-of-8 decoder q0 q1 q2 q3 q4 q5 q6 q7 12 11 10 9 7 6 5 4 a0 a1 a2 le mr d 13 15 14 3 2 1 fig 4. pin con?guration 74ahc259 74ahct259 a0 v cc a1 mr a2 le q0 d q1 q7 q2 q6 q3 q5 gnd q4 001aai126 1 2 3 4 5 6 7 8 10 9 12 11 14 13 16 15 table 2. pin description symbol pin description a0 1 address input a1 2 address input a2 3 address input q0 4 latch output q1 5 latch output q2 6 latch output q3 7 latch output gnd 8 ground (0 v) q4 9 latch output q5 10 latch output
74ahc_ahct259_2 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 02 15 may 2008 4 of 17 nxp semiconductors 74ahc259; 74ahct259 8-bit addressable latch 6. functional description [1] h = high voltage level; l = low voltage level; x = dont care; d = high or low data one set-up time prior to the low-to-high le transition; q = lower case letter indicates the state of the referenced input one set-up time prior to the low-to-high transition. q6 11 latch output q7 12 latch output d 13 data input le 14 latch enable input (active low) mr 15 conditional reset input (active low) v cc 16 supply voltage table 2. pin description continued symbol pin description table 3. function table [1] operating mode input output mr le d a0 a1 a2 q0 q1 q2 q3 q4 q5 q6 q7 reset (clear) l h xxxx llllllll demultiplexer (active high 8-channel) decoder (when d = h) lldlllq=d lllllll dhlllq=dllllll dlhlllq=dlllll dhhllllq=dllll dllh llllq=dlll dhlhlllllq=dll dlhhllllllq=dl dhhhlllllllq=d memory (no action) h h xxxxq 0 q 1 q 2 q 3 q 4 q 5 q 6 q 7 addressable latch h ldlllq=dq 1 q 2 q 3 q 4 q 5 q 6 q 7 dhllq 0 q=d q 2 q 3 q 4 q 5 q 6 q 7 dlhlq 0 q 1 q=d q 3 q 4 q 5 q 6 q 7 d hhl q 0 q 1 q 2 q=d q 4 q 5 q 6 q 7 dllhq 0 q 1 q 2 q 3 q=d q 5 q 6 q 7 dhlhq 0 q 1 q 2 q 3 q 4 q=d q 6 q 7 d l hhq 0 q 1 q 2 q 3 q 4 q 5 q=d q 7 hhhhq 0 q 1 q 2 q 3 q 4 q 5 q 6 q=d
74ahc_ahct259_2 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 02 15 may 2008 5 of 17 nxp semiconductors 74ahc259; 74ahct259 8-bit addressable latch [1] h = high voltage level; l = low voltage level. 7. limiting values [1] the input and output voltage ratings may be exceeded if the input and output current ratings are observed. [2] for so16 packages: above 70 c the value of p tot derates linearly at 8 mw/k. for tssop16 packages: above 60 c the value of p tot derates linearly at 5.5 mw/k. 8. recommended operating conditions table 4. operating mode select table [1] le mr mode l h addressable latch h h memory l l active high 8-channel demultiplexer h l reset table 5. limiting values in accordance with the absolute maximum rating system (iec 60134). voltages are referenced to gnd (ground = 0 v). symbol parameter conditions min max unit v cc supply voltage - 0.5 +7.0 v v i input voltage - 0.5 +7.0 v i ik input clamping current v i < - 0.5 v [1] - 20 - ma i ok output clamping current v o < - 0.5 v or v o > v cc + 0.5 v [1] - 20 +20 ma i o output current v o = - 0.5 v to (v cc + 0.5 v) - 25 +25 ma i cc supply current - +75 ma i gnd ground current - 75 - ma t stg storage temperature - 65 +150 c p tot total power dissipation t amb = - 40 c to +125 c [2] - 500 mw table 6. operating conditions symbol parameter conditions min typ max unit 74ahc259 v cc supply voltage 2.0 5.0 5.5 v v i input voltage 0 - 5.5 v v o output voltage 0 - v cc v t amb ambient temperature - 40 +25 +125 c d t/ d v input transition rise and fall rate v cc = 3.0 v to 3.6 v - - 100 ns/v v cc = 4.5 v to 5.5 v - - 20 ns/v 74ahct259 v cc supply voltage 4.5 5.0 5.5 v v i input voltage 0 - 5.5 v v o output voltage 0 - v cc v t amb ambient temperature - 40 +25 +125 c d t/ d v input transition rise and fall rate v cc = 4.5 v to 5.5 v - - 20 ns/v
74ahc_ahct259_2 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 02 15 may 2008 6 of 17 nxp semiconductors 74ahc259; 74ahct259 8-bit addressable latch 9. static characteristics table 7. static characteristics at recommended operating conditions; voltages are referenced to gnd (ground = 0 v). symbol parameter conditions 25 c - 40 c to +85 c - 40 c to +125 c unit min typ max min max min max 74ahc259 v ih high-level input voltage v cc = 2.0 v 1.5 - - 1.5 - 1.5 - v v cc = 3.0 v 2.1 - - 2.1 - 2.1 - v v cc = 5.5 v 3.85 - - 3.85 - 3.85 - v v il low-level input voltage v cc = 2.0 v - - 0.5 - 0.5 - 0.5 v v cc = 3.0 v - - 0.9 - 0.9 - 0.9 v v cc = 5.5 v - - 1.65 - 1.65 - 1.65 v v oh high-level output voltage v i = v ih or v il i o = - 50 m a; v cc = 2.0 v 1.9 2.0 - 1.9 - 1.9 - v i o = - 50 m a; v cc = 3.0 v 2.9 3.0 - 2.9 - 2.9 - v i o = - 50 m a; v cc = 4.5 v 4.4 4.5 - 4.4 - 4.4 - v i o = - 4.0 ma; v cc = 3.0 v 2.58 - - 2.48 - 2.40 - v i o = - 8.0 ma; v cc = 4.5 v 3.94 - - 3.80 - 3.70 - v v ol low-level output voltage v i = v ih or v il i o = 50 m a; v cc = 2.0 v - 0 0.1 - 0.1 - 0.1 v i o = 50 m a; v cc = 3.0 v - 0 0.1 - 0.1 - 0.1 v i o = 50 m a; v cc = 4.5 v - 0 0.1 - 0.1 - 0.1 v i o = 4.0 ma; v cc = 3.0 v - - 0.36 - 0.44 - 0.55 v i o = 8.0 ma; v cc = 4.5 v - - 0.36 - 0.44 - 0.55 v i i input leakage current v i = 5.5 v or gnd; v cc = 0 v to 5.5 v - - 0.1 - 1.0 - 2.0 m a i cc supply current v i =v cc or gnd; i o = 0 a; v cc = 5.5 v - - 4.0 - 40 - 80 m a c i input capacitance v i =v cc or gnd - 3 10 - 10 - 10 pf c o output capacitance -4- - - - -pf 74ahct259 v ih high-level input voltage v cc = 4.5 v to 5.5 v 2.0 - - 2.0 - 2.0 - v v il low-level input voltage v cc = 4.5 v to 5.5 v - - 0.8 - 0.8 - 0.8 v v oh high-level output voltage v i = v ih or v il ; v cc = 4.5 v i o = - 50 m a 4.4 4.5 - 4.4 - 4.4 - v i o = - 8.0 ma 3.94 - - 3.80 - 3.70 - v v ol low-level output voltage v i = v ih or v il ; v cc = 4.5 v i o = 50 m a - 0 0.1 - 0.1 - 0.1 v i o = 8.0 ma - - 0.36 - 0.44 - 0.55 v
74ahc_ahct259_2 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 02 15 may 2008 7 of 17 nxp semiconductors 74ahc259; 74ahct259 8-bit addressable latch 10. dynamic characteristics i i input leakage current v i = 5.5 v or gnd; v cc = 0 v to 5.5 v - - 0.1 - 1.0 - 2.0 m a i cc supply current v i =v cc or gnd; i o = 0 a; v cc = 5.5 v - - 4.0 - 40 - 80 m a d i cc additional supply current per input pin; v i =v cc - 2.1 v; other pins at v cc or gnd; i o = 0 a; v cc = 4.5 v to 5.5 v - - 1.35 - 1.5 - 1.5 ma c i input capacitance v i =v cc or gnd - 3 10 - 10 - 10 pf c o output capacitance -4- - - - -pf table 7. static characteristics continued at recommended operating conditions; voltages are referenced to gnd (ground = 0 v). symbol parameter conditions 25 c - 40 c to +85 c - 40 c to +125 c unit min typ max min max min max table 8. dynamic characteristics voltages are referenced to gnd (ground = 0 v); for test circuit see figure 11 . symbol parameter conditions 25 c - 40 c to +85 c - 40 c to +125 c unit min typ [1] max min max min max 74ahc259 t pd propagation delay d to qn; see figure 5 [2] v cc = 3.0 v to 3.6 v c l = 15 pf - 5.8 11.5 1.0 13.5 1.0 15.0 ns c l = 50 pf - 7.3 14.5 1.0 17.0 1.0 18.5 ns v cc = 4.5 v to 5.5 v c l = 15 pf - 4.1 7.5 1.0 9.0 1.0 10.0 ns c l = 50 pf - 5.3 9.5 1.0 11.0 1.0 12.0 ns an to qn; see figure 6 [2] v cc = 3.0 v to 3.6 v c l = 15 pf - 7.5 14.5 1.0 17.0 1.0 18.5 ns c l = 50 pf - 9.1 18.0 1.0 21.0 1.0 23.0 ns v cc = 4.5 v to 5.5 v c l = 15 pf - 5.3 9.5 1.0 11.5 1.0 12.5 ns c l = 50 pf - 6.5 11.5 1.0 13.5 1.0 15.0 ns le to qn; see figure 7 [2] v cc = 3.0 v to 3.6 v c l = 15 pf - 6.2 12.0 1.0 14.0 1.0 15.2 ns c l = 50 pf - 7.7 15.5 1.0 17.5 1.0 19.0 ns v cc = 4.5 v to 5.5 v c l = 15 pf - 4.3 8.0 1.0 9.5 1.0 10.5 ns c l = 50 pf - 5.5 10.0 1.0 11.5 1.0 12.5 ns
74ahc_ahct259_2 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 02 15 may 2008 8 of 17 nxp semiconductors 74ahc259; 74ahct259 8-bit addressable latch t pd propagation delay mr to qn; see figure 8 [3] v cc = 3.0 v to 3.6 v c l = 15 pf - 5.4 10.5 1.0 12.5 1.0 13.5 ns c l = 50 pf - 7.0 13.5 1.0 15.5 1.0 17.0 ns v cc = 4.5 v to 5.5 v c l = 15 pf - 3.9 7.0 1.0 8.5 1.0 9.5 ns c l = 50 pf - 5.1 9.0 1.0 10.5 1.0 11.5 ns t w pulse width le high or low; see figure 7 v cc = 3.0 v to 3.6 v 5.0 - - 5.0 - 5.0 - ns v cc = 4.5 v to 5.5 v 5.0 - - 5.0 - 5.0 - ns mr low; see figure 8 v cc = 3.0 v to 3.6 v 5.0 - - 5.0 - 5.0 - ns v cc = 4.5 v to 5.5 v 5.0 - - 5.0 - 5.0 - ns t su set-up time d, an to le; see figure 9 and figure 10 v cc = 3.0 v to 3.6 v 4.0 - - 4.0 - 4.0 - ns v cc = 4.5 v to 5.5 v 4.0 - - 4.0 - 4.0 - ns t h hold time d, an to le; see figure 9 and figure 10 v cc = 3.0 v to 3.6 v 1.0 - - 1.0 - 1.0 - ns v cc = 4.5 v to 5.5 v 1.0 - - 1.0 - 1.0 - ns c pd power dissipation capacitance f i = 1 mhz; v i = gnd to v cc [4] -13- - - - -pf 74ahct259; v cc = 4.5 v to 5.5 v t pd propagation delay d to qn; see figure 5 [2] c l = 15 pf - 4.1 7.5 1.0 9.0 1.0 10.0 ns c l = 50 pf - 5.4 9.5 1.0 11.0 1.0 12.0 ns an to qn; see figure 6 [2] c l = 15 pf - 5.5 9.5 1.0 11.5 1.0 12.5 ns c l = 50 pf - 6.6 12.0 1.0 14.0 1.0 15.5 ns le to qn; see figure 7 [2] c l = 15 pf - 4.3 8.0 1.0 9.5 1.0 10.4 ns c l = 50 pf - 5.5 10.0 1.0 12.0 1.0 13.0 ns mr to qn; see figure 8 [3] c l = 15 pf - 3.9 7.0 1.0 8.5 1.0 9.5 ns c l = 50 pf - 5.1 9.0 1.0 10.5 1.0 11.5 ns t w pulse width le high or low; see figure 7 5.0 - - 5.0 - 5.0 - ns mr low; see figure 8 5.0 - - 5.0 - 5.0 - ns table 8. dynamic characteristics continued voltages are referenced to gnd (ground = 0 v); for test circuit see figure 11 . symbol parameter conditions 25 c - 40 c to +85 c - 40 c to +125 c unit min typ [1] max min max min max
74ahc_ahct259_2 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 02 15 may 2008 9 of 17 nxp semiconductors 74ahc259; 74ahct259 8-bit addressable latch [1] typical values are measured at nominal supply voltage (v cc = 3.3 v and v cc = 5.0 v). [2] t pd is the same as t plh and t phl . [3] t pd is the same as t phl only. [4] c pd is used to determine the dynamic power dissipation (p d in m w). p d =c pd v cc 2 f i n+ s (c l v cc 2 f o ) where: f i = input frequency in mhz; f o = output frequency in mhz; c l = output load capacitance in pf; v cc = supply voltage in v; n = number of inputs switching; s (c l v cc 2 f o ) = sum of the outputs. 11. waveforms t su set-up time d, an to le; see figure 9 and figure 10 4.0 - - 4.0 - 4.0 - ns t h hold time d, an to le; see figure 9 and figure 10 1.0 - - 1.0 - 1.0 - ns c pd power dissipation capacitance f i = 1 mhz; v i = gnd to v cc [4] -17- - - - -pf table 8. dynamic characteristics continued voltages are referenced to gnd (ground = 0 v); for test circuit see figure 11 . symbol parameter conditions 25 c - 40 c to +85 c - 40 c to +125 c unit min typ [1] max min max min max measurement points are given in t ab le 9 . v ol and v oh are typical voltage output levels that occur with the output load. fig 5. data input to output propagation delays 001aah123 d input qn output t phl t plh gnd v cc v m v m v oh v ol
74ahc_ahct259_2 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 02 15 may 2008 10 of 17 nxp semiconductors 74ahc259; 74ahct259 8-bit addressable latch measurement points are given in t ab le 9 . v ol and v oh are typical voltage output levels that occur with the output load. fig 6. address input to output propagation delays 001aah122 an input qn output t phl t plh gnd v cc v m v m v oh v ol measurement points are given in t ab le 9 . v ol and v oh are typical voltage output levels that occur with the output load. fig 7. enable input to output propagation delays and pulse width 001aah121 le input qn output t phl t plh t w v m v oh v cc gnd v cc gnd v ol v m d input measurement points are given in t ab le 9 . v ol and v oh are typical voltage output levels that occur with the output load. fig 8. conditional reset input to output propagation delays 001aah124 mr input qn output t phl t w v m v oh v cc gnd v ol v m
74ahc_ahct259_2 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 02 15 may 2008 11 of 17 nxp semiconductors 74ahc259; 74ahct259 8-bit addressable latch measurement points are given in t ab le 9 . the shaded areas indicate when the input is permitted to change for predictable output performance. v ol and v oh are typical voltage output levels that occur with the output load. fig 9. data input to latch enable input set-up and hold times 001aah125 gnd gnd t h t su t h t su v m v m v m v cc v oh v ol v cc qn output q = d q = d le input d input measurement points are given in t ab le 9 . the shaded areas indicate when the input is permitted to change for predictable output performance. v ol and v oh are typical voltage output levels that occur with the output load. fig 10. address input to latch enable input set-up and hold times 001aah126 v m address stable v m t h t su v cc gnd v cc gnd le input an input table 9. measurement points type input output v m v m 74ahc259 0.5 v cc 0.5 v cc 74ahct259 1.5 v 0.5 v cc
74ahc_ahct259_2 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 02 15 may 2008 12 of 17 nxp semiconductors 74ahc259; 74ahct259 8-bit addressable latch test data is given in t ab le 10 . de?nitions test circuit: r t = termination resistance should be equal to output impedance z o of the pulse generator. c l = load capacitance including jig and probe capacitance. fig 11. load circuitry for measuring switching times 001aah768 t w t w t r t r t f v m v i negative pulse gnd v i positive pulse gnd 10 % 90 % 90 % 10 % v m v m v m t f v cc dut r t v i v o c l g table 10. test data type input load test v i t r , t f c l 74ahc259 v cc 3.0 ns 15 pf, 50 pf t plh , t phl 74ahct259 3.0 v 3.0 ns 15 pf, 50 pf t plh , t phl
74ahc_ahct259_2 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 02 15 may 2008 13 of 17 nxp semiconductors 74ahc259; 74ahct259 8-bit addressable latch 12. package outline fig 12. package outline sot109-1 (so16) x w m q a a 1 a 2 b p d h e l p q detail x e z e c l v m a (a ) 3 a 8 9 1 16 y pin 1 index unit a max. a 1 a 2 a 3 b p cd (1) e (1) (1) eh e ll p qz y w v q references outline version european projection issue date iec jedec jeita mm inches 1.75 0.25 0.10 1.45 1.25 0.25 0.49 0.36 0.25 0.19 10.0 9.8 4.0 3.8 1.27 6.2 5.8 0.7 0.6 0.7 0.3 8 0 o o 0.25 0.1 dimensions (inch dimensions are derived from the original mm dimensions) note 1. plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included. 1.0 0.4 sot109-1 99-12-27 03-02-19 076e07 ms-012 0.069 0.010 0.004 0.057 0.049 0.01 0.019 0.014 0.0100 0.0075 0.39 0.38 0.16 0.15 0.05 1.05 0.041 0.244 0.228 0.028 0.020 0.028 0.012 0.01 0.25 0.01 0.004 0.039 0.016 0 2.5 5 mm scale so16: plastic small outline package; 16 leads; body width 3.9 mm sot109-1
74ahc_ahct259_2 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 02 15 may 2008 14 of 17 nxp semiconductors 74ahc259; 74ahct259 8-bit addressable latch fig 13. package outline sot403-1 (tssop16) unit a 1 a 2 a 3 b p cd (1) e (2) (1) eh e ll p qz y w v q references outline version european projection issue date iec jedec jeita mm 0.15 0.05 0.95 0.80 0.30 0.19 0.2 0.1 5.1 4.9 4.5 4.3 0.65 6.6 6.2 0.4 0.3 0.40 0.06 8 0 o o 0.13 0.1 0.2 1 dimensions (mm are the original dimensions) notes 1. plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. plastic interlead protrusions of 0.25 mm maximum per side are not included. 0.75 0.50 sot403-1 mo-153 99-12-27 03-02-18 w m b p d z e 0.25 18 16 9 q a a 1 a 2 l p q detail x l (a ) 3 h e e c v m a x a y 0 2.5 5 mm scale tssop16: plastic thin shrink small outline package; 16 leads; body width 4.4 mm sot403-1 a max. 1.1 pin 1 index
74ahc_ahct259_2 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 02 15 may 2008 15 of 17 nxp semiconductors 74ahc259; 74ahct259 8-bit addressable latch 13. abbreviations 14. revision history table 11. abbreviations acronym description cdm charged device model cmos complementary metal-oxide semiconductor dut device under test esd electrostatic discharge hbm human body model lsttl low-power schottky transistor-transistor logic mm machine model table 12. revision history document id release date data sheet status change notice supersedes 74ahc_ahct259_2 20080515 product data sheet - 74ahc_ahct259_1 modi?cations: ? the format of this data sheet has been redesigned to comply with the new identity guidelines of nxp semiconductors. ? legal texts have been adapted to the new company name where appropriate. ? t ab le 6 : the conditions for input leakage current have been changed. 74ahc_ahct259_1 20000314 product speci?cation - -
74ahc_ahct259_2 ? nxp b.v. 2008. all rights reserved. product data sheet rev. 02 15 may 2008 16 of 17 nxp semiconductors 74ahc259; 74ahct259 8-bit addressable latch 15. legal information 15.1 data sheet status [1] please consult the most recently issued document before initiating or completing a design. [2] the term short data sheet is explained in section de?nitions. [3] the product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple dev ices. the latest product status information is available on the internet at url http://www .nxp .com . 15.2 de?nitions draft the document is a draft version only. the content is still under internal review and subject to formal approval, which may result in modi?cations or additions. nxp semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. short data sheet a short data sheet is an extract from a full data sheet with the same product type number(s) and title. a short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. for detailed and full information see the relevant full data sheet, which is available on request via the local nxp semiconductors sales of?ce. in case of any inconsistency or con?ict with the short data sheet, the full data sheet shall prevail. 15.3 disclaimers general information in this document is believed to be accurate and reliable. however, nxp semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. right to make changes nxp semiconductors reserves the right to make changes to information published in this document, including without limitation speci?cations and product descriptions, at any time and without notice. this document supersedes and replaces all information supplied prior to the publication hereof. suitability for use nxp semiconductors products are not designed, authorized or warranted to be suitable for use in medical, military, aircraft, space or life support equipment, nor in applications where failure or malfunction of an nxp semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. nxp semiconductors accepts no liability for inclusion and/or use of nxp semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customers own risk. applications applications that are described herein for any of these products are for illustrative purposes only. nxp semiconductors makes no representation or warranty that such applications will be suitable for the speci?ed use without further testing or modi?cation. limiting values stress above one or more limiting values (as de?ned in the absolute maximum ratings system of iec 60134) may cause permanent damage to the device. limiting values are stress ratings only and operation of the device at these or any other conditions above those given in the characteristics sections of this document is not implied. exposure to limiting values for extended periods may affect device reliability. terms and conditions of sale nxp semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www .nxp .com/pro? le/ter ms , including those pertaining to warranty, intellectual property rights infringement and limitation of liability, unless explicitly otherwise agreed to in writing by nxp semiconductors. in case of any inconsistency or con?ict between information in this document and such terms and conditions, the latter will prevail. no offer to sell or license nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. 15.4 trademarks notice: all referenced brands, product names, service names and trademarks are the property of their respective owners. 16. contact information for more information, please visit: http://www .nxp.com for sales of?ce addresses, please send an email to: salesad dresses@nxp.com document status [1] [2] product status [3] de?nition objective [short] data sheet development this document contains data from the objective speci?cation for product development. preliminary [short] data sheet quali?cation this document contains data from the preliminary speci?cation. product [short] data sheet production this document contains the product speci?cation.
nxp semiconductors 74ahc259; 74ahct259 8-bit addressable latch ? nxp b.v. 2008. all rights reserved. for more information, please visit: http://www.nxp.com for sales office addresses, please send an email to: salesaddresses@nxp.com date of release: 15 may 2008 document identifier: 74ahc_ahct259_2 please be aware that important notices concerning this document and the product(s) described herein, have been included in section legal information. 17. contents 1 general description . . . . . . . . . . . . . . . . . . . . . . 1 2 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 3 ordering information . . . . . . . . . . . . . . . . . . . . . 2 4 functional diagram . . . . . . . . . . . . . . . . . . . . . . 2 5 pinning information . . . . . . . . . . . . . . . . . . . . . . 3 5.1 pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 5.2 pin description . . . . . . . . . . . . . . . . . . . . . . . . . 3 6 functional description . . . . . . . . . . . . . . . . . . . 4 7 limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 5 8 recommended operating conditions. . . . . . . . 5 9 static characteristics. . . . . . . . . . . . . . . . . . . . . 6 10 dynamic characteristics . . . . . . . . . . . . . . . . . . 7 11 waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 12 package outline . . . . . . . . . . . . . . . . . . . . . . . . 13 13 abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 15 14 revision history . . . . . . . . . . . . . . . . . . . . . . . . 15 15 legal information. . . . . . . . . . . . . . . . . . . . . . . 16 15.1 data sheet status . . . . . . . . . . . . . . . . . . . . . . 16 15.2 de?nitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 15.3 disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 15.4 trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 16 contact information. . . . . . . . . . . . . . . . . . . . . 16 17 contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

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